The technology disclosed relates to tracking and analyzing internet traffic flows. In particular, it relates to reducing effective cycle time in read and write operations of memory modules used in storing statistics from tracking and analyzing internet traffic flows.
When testing the internet traffic, thousands or millions of flows may be tracked and analyzed. Statistics about the individual flows, such as frame and byte counters, and error measurements, may be counted and stored in high density memory modules such as DRAMs (dynamic random access memory). Each flow contains a stream of frames. Each frame contains a number of bytes. For each frame, read and write operations are performed. To properly perform certain measurements, parameters and statistics are allowed at least one read and one write operation per frame. The shortest frame supported for a given test can be dependent on bandwidths of the memory modules. High density memory modules such as DRAMs typically have multiple banks, and each bank may have millions of memory bits. High density memory modules may be suitable for storing the statistics from testing internet, but they typically have a time penalty when accessing different rows within the same bank. This cycle time limitation can limit the minimum frame time supported by the system, and thus impact the overall system performance.
An opportunity arises to provide a method to reduce the effective cycle time in accessing memory modules used in storing statistics from tracking and analyzing internet traffic flows.